1. Field of the Invention
The present invention relates to an evaluation system for evaluating the performance of an analog-digital converter (A-D converter) which converts an analog signal into a digital signal or a digital-analog converter (D-A converter) which converts a digital signal into an analog signal, and more particularly, to a performance evaluation system for evaluating the effective number of bits of an A-D converter or D-A converter which is implemented by a single semiconductor integrated circuit or a combination of a plurality of semiconductor integrated circuits.
2. Description of the Related Art
A method of evaluating an A-D converter (hereinafter, referred to as ADC) is categorized into a static characteristic evaluation method and a dynamic characteristic evaluation method. According to the static characteristic evaluation method, a precisely defined direct current (dc) voltage is applied to an ADC which is a device under test (DUT), and a response from the ADC is observed, and thereafter, xe2x80x9ca difference between the transition voltage of an actual ADC and the transition voltage of an ideal ADCxe2x80x9d is estimated in a computer or the like using the differential nonlinearity (DNL) or the like.
The differential nonlinearity (DNL) in this case is a result of the comparison of a difference (actual step width) between the upper limit amplitudes of an analog signal which causes an ADC to output adjacent quantized codes therefrom when applied to the ADC, with an ideal step width which corresponds to 1 LSB, and enables a localized fault or defect which depends on a particular code to be detected. That is, DNL for an ADC is defined as follows:
DNL=Ain(Qm+1)xe2x88x92Ain(Qm)xe2x88x921[LSB]xe2x80x83xe2x80x83(1)
where Qm+1 and Qm are two adjacent quantized codes and Ain(Qn) is the upper limit of the amplitude of an analog signal which corresponds to the quantized code Qn. For example, if xe2x80x9cthe difference between adjacent transition amplitudesxe2x80x9d remains constant and equals the step size (width) corresponding to 1 LSB, then DNL is zero.
However, the static characteristic evaluation method cannot measure or determine the nonlinearity of an ADC which is a device under test which depends on the frequency of a signal to be applied to the ADC.
According to the dynamic characteristic evaluation method, a periodic signal is applied to an ADC which is a device under test, and a response from the ADC is observed, and thereafter, xe2x80x9ca difference between the transition voltage of an actual ADC and the transition voltage of an ideal ADCxe2x80x9d is estimated in a computer or the like.
This method has an advantage that a characteristic which closely approximates an actual operation of the ADC to be tested can be estimated. Particularly, dynamic characteristic evaluation techniques which utilize a sine wave (sinusoidal wave) as an input signal include a histogram approach, an FFT approach and a curve fitting approach as mentioned below.
(a) In the histogram approach, a histogram is plotted against each quantized code from a digital waveform of the response from the ADC. A difference between the histogram of an actual ADC and the histogram of an ideal ADC is then determined and divided by the histogram of the ideal ADC to estimate DNL. The normalization of the difference in the histograms or its division by the histogram of the ideal ADC accounts for a non-uniform distribution of the sine wave histogram.
(b) In the FFT approach, a digital signal representing the response of the ADC is Fourier transformed as by FFT (fast Fourier transform), and is separated in the frequency domain into a signal (namely, a frequency spectrum of the sine wave applied) and noises (namely, a spectrum of quantization noises or a sum of spectra other than the frequency of the sine wave applied), thus determining a signal-to-noise ratio (SNR).
For example, as shown in FIG. 17A, a sine wave signal from a sine wave generator 11 is passed through a low pass filter (LPF) 12 to eliminate unwanted components therefrom before it is fed to a sample-and-hold circuit 13 where the sine wave signal is sampled periodically and held therein for feeding to an ADC 14 under test. A response output from the ADC 14 is fed to an FFT unit 15 where it is subject to the fast Fourier transform to be transformed into a signal in the frequency domain, which is then fed to an SNR estimator 16. On the basis of a result of the FFT as illustrated in FIG. 17B, the SNR estimator 16 determines the signal-to-noise ratio SNR by dividing the sine waveform signal component Gss(f0) by the noise component:       ∑          f      ≠              f        0              ⁢            G      nn        ⁡          (      f      )      
If the quantization noise increases in the ADC 14 because of fault, the signal-to-noise ratio SNR is degraded, increasing the number of bits among the total number of bits in the ADC 14 which are influenced by the quantization noise. It is then possible to estimate the effective number of bits (ENOB) of the tested ADC on the basis of the signal-to-noise ratio observed. The effective number of bits (ENOB) of the tested ADC can be given by the following equation (2).                     ENOB        =                                                            SNR                ⁡                                  [                  dB                  ]                                            -              1.76                        6.02                    ⁡                      [            bits            ]                                              (        2        )            
In this case, by changing the frequency f0 of the sine wave signal applied, the frequency dependency of ENOB can be measured or determined.
(c) In the curve fitting approach using the sine wave, parameters (such as frequency, phase, amplitude, offset etc.) of an ideal sine wave are chosen so that the square error between a sampled digital signal and the ideal sine wave is minimized. An rms (root-mean-square) error determined in this manner is compared against the rms error of the ideal ADC having the same number of bits to estimate the effective number of bits.
Means for generating an analog signal such as a sine wave is described in detail in xe2x80x9cTheory and Application of Digital Signal Processingxe2x80x9d by Lawrence R. Rabiner and Bernard Gold; Prentice-Hall, 1975, in particular, xe2x80x9c9.12: Hardware realization of a Digital Frequency Synthesizerxe2x80x9d, for example.
A problem with the use of the histogram approach mentioned in the above paragraph (a) to estimate the DNL of an ADC with a high precision is a very long time needed for the determination. By way of example, an estimation of the DNL for an 8-bit ADC with a reliability of 99% and for an interval width of 0.01 bit requires 268,000 samples. For a 12-bit ADC, as many as 4,200,000 samples are required. (See, for example, xe2x80x9cFull-Speed Testing of A/D Convertersxe2x80x9d by Joey Doernberg, Hae-Seung Lee and David A. Hodges, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, pp. 820-827, 1984.) When the ADC under test exhibits hysteresis, it is likely that any fault therein cannot be detected by using the histogram approach.
Here it is assumed that when an input signal crosses a given level with a positive gradient, a corresponding code width is enlarged, increasing the number of observations, while when the input signal crosses the given level with a negative gradient, the corresponding code width shrinks, decreasing the number of observations.
According to the histogram approach, no distinction is made in the direction in which the input signal changes, and accordingly, the number of observations for the positive gradient and the number of observations for the negative gradient are added together in the number of observations. As a result, an increase and a decrease in the number of observations cancel each other, and the code width will be one close to a code width for a fault-free ideal ADC. (See, for example, xe2x80x9cClassical Tests are inadequate for Modern High-Speed Convertersxe2x80x9d by Ray K. Ushani, Datel Application Notes AN-5, 1991.) As a consequence, the DNL which can be estimated with the histogram approach is a result of comparison of a difference in mean values of output code width against the ideal step size corresponding to 1 LSB. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC. (See, for example, the paper by Joey Doernberg, Hae-Seung Lee and David A. Hodges.)
A problem with the estimation of the effective number of bits by the FTT approach mentioned in the above paragraph (b) will be considered. To enable an accurate observation of the noise spectrum from the ADC under test using the FTT approach, it is necessary that the standard deviation       ϵ    ⁡          [                        G          ^                aa            ]        ≈      1          N      
made sufficiently small. (See, for example, J. S. Bendat and A. G. Piersol, 1986.) The number of samples N must be increased at this end. When the number of samples is increased by a factor of 4, the noise level will be 6 dB lower. The computation of an FFT requires a number of real number multiplications, which is represented by       N    ·                  log        2            ⁡              [                  N          2                ]              -  4
and a number of real number additions, which is represented by:
3/2Nxc2x7(log2[N]+1)xe2x88x9212
The ADC converts an analog signal into a digital output code in accordance with the amplitude of the input signal. If the Fourier transform of the output signal is used in evaluating the conversion characteristic of ADC, conversion defects that are localized in individual output codes cannot be separated. This is because defects present within different codes are added together as noise in calculating the rms error. Thus if there is no correlation between the defects and if different codes are influenced by them, these defects will be evaluated as xe2x80x9cpart of noise which coherently influences the same code.xe2x80x9d As a consequence, there is a likelihood that the number of effective bits may be underestimated. (See, for example, xe2x80x9cData-converters: Getting to know Dynamic Specsxe2x80x9d by Robert E. Leonard Jr., Datel Application Notes AN-3.) At the same time, an analysis of individual factors which cause a reduction in the effective number of bits such as DNL, integral nonlinearity (INL), aperture jitter or noise is prohibited. Thus, the effective number of bits which can be estimated by this approach is not an instantaneous value which corresponds to each output code, but is a mean value determined over the entire output codes. Moreover, there is a need to provide a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC in order to randomize the quantization error. (See, for example, xe2x80x9cIntegrated Analog-to-Digital and Digital-to-Analog Convertersxe2x80x9d by Rudy van der Plassche, Kluwer Academic Publishers, 1994.)
Finally, a problem with the curve fitting approach mentioned in the above paragraph (c) will be considered. With this approach, it is necessary to estimate the parameters of the ideal sine wave by the method of least squares.
(1) To estimate the frequency of the ideal sine wave, the Fourier transform takes place only for a single presumed frequency to determine the power. When the power reaches a maximal value, the frequency is estimated. The maximal value cannot be found unless the frequency estimation is repeated at least three times. Thus, this requires 9N (where N represents the number of samples) real number multiplications and (6Nxe2x88x923) real number additions.
(2) The estimation of the phase requires 2N real number multiplications, (2Nxe2x88x922) real number additions, one real number division and one calculation of arctangent.
(3) The estimation of the amplitude requires 2N real number multiplications, (2Nxe2x88x922) real number additions and one real number division.
Where the operation of the ADC under test largely departs from its normal operation or where the digital waveform from the ADC under test contains a reduced number of samples, the square error does not approach a given value if the calculation of the square error is effected while changing the parameter of the sine wave. Thus, the error diverges rather than converges. To give an example, since the variance of the frequency estimate is proportional to 1/N3, a sufficiently great number of samples, in excess of 4096 samples, are necessary to suppress the variance. The effective number of bits which can be estimated by this approach corresponds again to a mean value determined over the entire output codes. As a consequence, an analysis of individual factors such as harmonic distortion, noise or aperture jitter which causes a reduction in the effective number of bits is prohibited. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine-wave and the sampling frequency of the ADC. If the sampling frequency were an integral multiple of the frequency of the input sine wave, the input signal would become coherent to the sampling, with consequence that only a specific quantization level would be tested. (See, for example, the paper by Ray K. Ushani.)
Problems with the prior art techniques for evaluation of dynamic characteristics of the ADC can be summarized as the following:
The DNL or the effective number of bits estimated according to any technique represents a mean value rather than an instantaneous value. Accordingly, it is difficult to estimate independently factors of a compounded fault. In the process of estimating the effective number of bits for an ADC which uses a sine wave as an input signal, a relationship other than an integral multiple must be established between the frequency of the input sine wave and the sampling frequency of the ADC. For this reason, an arbitrary frequency cannot be selected as the testing frequency. In addition, a very large number of samples are required for any technique chosen. Assuming a number of samples equal to 512, the volume of computation needed is as follows:
FFT approach: 4092 real number multiplications and 7668 real number additions;
curve fitting approach: 6656 real number multiplications and 4092 real number additions.
Like the case of the ADC, the method of evaluating the performance of a D-A converter (hereinafter, referred to as DAC) is also categorized into a static characteristic evaluation method and a dynamic characteristic evaluation method. According to the static characteristic evaluation method, a ramp waveform digital signal pattern is applied to a DAC which is a device under test (DUT), and a response from the DAC is observed, and thereafter, xe2x80x9ca difference between the transition voltage of an actual DAC and the transition voltage of an ideal DACxe2x80x9d is estimated in a computer or the like using the differential nonlinearity (DNL) or the like.
The differential nonlinearity (DNL) in this case is a result of the comparison of a difference in the analog outputs (actual step width) as adjacent digital codes are input to the DAC against an ideal step width which corresponds to 1 LSB, and permits a localized defect which depends on a particular code to be detected. That is, DNL for the DAC is defined as follows:
DNL=Sout(Cm+1)xe2x88x92Sout(Cm)xe2x88x921[LSB]xe2x80x83xe2x80x83(3)
where Cm+1 and Cm are two adjacent digital codes which are inputted to the DAC, and Sout(Cn) represents an analog output signal corresponding to the digital code Cn. For example, if all of xe2x80x9cthe difference between analog outputs for adjacent digital codesxe2x80x9d remain constant and equal the step size (width) corresponding to 1 LSB, then DNL equals to zero.
However, the static characteristic evaluation method cannot measure or determine the nonlinearity of a DAC, which depends on the frequency of a signal to be applied to the DAC.
According to the dynamic characteristic evaluation method, a periodic signal is applied to a DAC which is a device under test, and a response from the DAC is observed, and thereafter, xe2x80x9ca difference between the transition voltage of an actual DAC and the transition voltage of an ideal DACxe2x80x9d is estimated in a computer or the like.
This method has an advantage that a characteristic which closely approximates an actual operation of the DAC to be tested can be estimated. In a similar manner to the case of the ADC, dynamic characteristic evaluation techniques which utilize a sine wave (sinusoidal wave) as an input signal particularly include a histogram approach, an FFT approach and a curve fitting approach mentioned below.
(a) In the histogram approach, a histogram is plotted against each quantized code from an analog waveform of the response from the DAC, which is digitalized by a high precision ADC. A difference between the histogram of an actual DAC and the histogram of an ideal DAC is then determined and is then divided by the histogram of the ideal DAC to estimate DNL. A normalization of the difference in the histograms by its division by the histogram of the ideal DAC accounts for a non-uniform distribution of the sine wave histogram.
(b) In the FFT approach, an analog waveform representing the response of the DAC is digitalized with a high precision ADC and subjected to a Fourier transform as by FFT, and is separated in the frequency domain into a signal (namely, a frequency spectrum of the sine wave applied) and noises (namely, a sum of spectra other than sine wave applied), thus determining a signal-to-noise ratio (SNR).
For example, as shown in FIG. 25, a digital signal of a sine wave from a pattern generator 111 is applied to a DAC under test (DUT) 112, and an analog signal delivered from the DAC 112 is supplied to a high precision ADC 113, which converts it into a digital signal of a high precision. This digital signal is fed to an FFT unit 114 where a fast Fourier transform takes place to transform it into a signal in a frequency domain, whereupon it is fed to an SNR (signal-to-noise ratio) estimator 115. On the basis of a result of the FFT as illustrated in FIG. 17B, the SNR estimator 115 determines the signal-to-noise ratio SNR by dividing the sine wave signal component Gss(f0) applied to the DAC 112 by the noise component:       ∑          f      ≠              f        0              ⁢            G      nn        ⁡          (      f      )      
If the quantization noise or conversion error increases in the DAC 112 because of fault, the signal-to-noise ratio SNR is degraded, increasing the number of bits among the total number of bits in the DAC 112 which are influenced by the quantization noise or conversion error. It is then possible to estimate the effective number of bits (ENOB) of the tested DAC on the basis of the signal-to-noise ratio observed. The effective number of bits (ENOB) of the DAC can be given by the following equation (4).                     ENOB        =                                                            SNR                ⁡                                  [                  dB                  ]                                            -              1.76                        6.02                    ⁡                      [            bits            ]                                              (        4        )            
In this case, by changing the frequency f0 of the sine wave signal applied, the frequency dependency of ENOB can be measured or determined.
(c) In the curve fitting approach with the sine wave, parameters (such as frequency, phase, amplitude or offset) of an ideal sine wave are chosen so that the square error between a sampled digital signal and the ideal sine wave is minimized. An rms (root-mean-square) error determined in this manner is compared against the rms error of the ideal DAC having the same number of bits to estimate the effective number of bits.
Means for generating an analog signal such as a sine wave is described in detail in xe2x80x9cTheory and Application of Digital Signal Processingxe2x80x9d by Lawrence R. Rabiner and Bernard Gold; Prentice-Hall, 1975, in particular, xe2x80x9c9.12: Hardware realization of a Digital Frequency Synthesizerxe2x80x9d, for example. By substituting a digital fitter for the analog filter shown in this literature, distortion components in the sine wave can be eliminated.
A problem with the use of the histogram approach mentioned in the above paragraph (a) to estimate the DNL of a DAC with a high precision is a very long time needed for the determination. By way of example, an estimation of the DNL for an 8bit DAC with a reliability of 99% and for an interval width of 0.01 bit requires 268,000 samples. For a 12-bit DAC, as many as 4,200,000 samples are required. (See, for example, xe2x80x9cFull-Speed Testing of A/D Convertersxe2x80x9d by Joey Doernberg, Hae-Seung Lee and David A. Hodges, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, pp. 820-827, 1984.) When the DAC under test has hysteresis, it is likely that any fault therein cannot be detected by using the histogram approach.
Here it is assumed that when an input signal crosses a given level with a positive gradient, a corresponding code width is enlarged, increasing the number of observations, while when the input signal crosses the given level with a negative gradient, the corresponding code width shrinks, decreasing the number of observations.
According to the histogram approach, no distinction is made in the direction in which the input signal changes, and accordingly, the number of observations for the positive gradient and the number of observations for the negative gradient are added together in the number of observations. Hence, an increase and a decrease in the number of observations cancel each other, and the code width will be one close to a code width for a fault-free ideal DAC. (See, for example, xe2x80x9cClassical Tests are inadequate for Modern High-Speed Convertersxe2x80x9d by Ray K. Ushani, Datel Application Notes AN-5, 1991.) As a consequence, the DNL which can be estimated with the histogram approach is a result of comparison of a difference in mean values of output code widths against the ideal step size corresponding to 1 LSB. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the DAC. (See, for example, the cited paper by Joey Doernberg, Hae-Seung Lee and David A. Hodges.)
A problem with the estimation of the effective number of bits by the FTT approach mentioned in the above paragraph (b) will be considered. To enable an accurate observation of the noise spectrum from the DAC under test using the FTT approach, it is necessary that the standard deviation       ϵ    ⁡          [                        G          ^                aa            ]        ≈      1          N      
be made sufficiently small. (See, for example, J. S. Bendat and A. G. Piersol, 1986.) The number of samples N must be increased at this end. When the number of samples is increased by a factor of 4, the noise level will be 6 dB lower. The computation of FFT requires a number of real number multiplications, which is represented by:       N    ·                  log        2            ⁡              [                  N          2                ]              -  4
and a number of real number additions, which is represented by:
3/2Nxc2x7(log2[N]+1)xe2x88x9212
The DAC converts a digital code in the input signal into an analog signal for delivery. If the Fourier transform of the output signal is used in evaluating the conversion characteristic of DAC conversion defects that are localized in individual input codes cannot be separated. This is because defects which correspond to respective different codes only will be added together as noise in calculating the rms error. Thus even if there is no correlation between the defects and if different analog signal level in the output are influenced by them, these defects will be evaluated as xe2x80x9cpart of the noise which coherently influences the same analog signalxe2x80x9d. As a consequence, there is a likelihood that the number of effective bits may be underestimated. (See, for example, xe2x80x9cData converters: Getting to know Dynamic Specsxe2x80x9d by Robert E. Leonard Jr., Datel Application Notes AN-3.) At the same time, an analysis of individual factors which cause a reduction in the effective number of bits such as DNL, integral nonlinearity (INL), glitch or noise is prohibited. Thus, the effective number of bits which can be estimated by this approach is not an instantaneous value which corresponds to each input code, but is a mean value determined over the entire output codes. Moreover, there is a need to provide a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the DAC in order to randomize the conversion error. (See, for example, xe2x80x9cIntegrated Analog-to-Digital and Digital-to-Analog Convertersxe2x80x9d by Rudy van der Plassche, Kluwer Academic Publishers, 1994.)
Finally, a problem with the curve fitting approach mentioned in the above paragraph (c) will be considered. With this approach, it is necessary to estimate the parameter of the ideal sine wave by the method of least squares.
(1) To estimate the frequency of the ideal sine wave, the Fourier transform takes place only for a single presumed frequency to determine the power. When the power reaches a maximal value, the frequency is estimated. The maximal value cannot be found unless the frequency estimation is repeated at least three times. Thus, this requires 9N (where N represents the number of samples) real number multiplications and (6Nxe2x88x923) real number additions.
(2) The estimation of the phase requires 2N real number multiplications, (2Nxe2x88x922) real number additions, one real number division and one calculation of arctangent.
(3) The estimation of the amplitude requires 2N real number multiplications, (2Nxe2x88x922) real number additions and one real number division.
Where the operation of the DAC under test largely departs from its normal operation or where the analog waveform from the DAC under test contains a reduced number of samples, the square error does not approach a given value if the calculation of the square error is repeated while changing the parameter of the sine wave. Thus, the error diverges rather than converges. To give an example, since the variance of the frequency estimate is proportional to 1/N3, a sufficiently great number of samples, in excess of 4096 samples, are necessary to suppress the variance. The effective number of bits which can be estimated by this approach also corresponds to a mean value determined over the entire input codes. As a consequence, an analysis of individual factors such as harmonic distortion, noise or glitch which causes a reduction in the effective number of bits is prohibited. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC. If the sampling frequency were an integral multiple of the frequency of the input sine wave, the input signal would be coherent to the sampling, with consequence that only a specific quantization level would be tested. (See, for example, the paper by Ray K. Ushani.)
Problems with the prior art technique for evaluation of dynamic characteristics of the DAC can be summarized as follows:
The DNL or the effective number of bits estimated according to any technique represents a mean value rather than an instantaneous value. Accordingly, it is difficult to estimate independently factors of a compounded fault. In the process of estimating the effective number of bits for a DAC which uses a sine wave as an input signal, a relationship other than an integral multiple must be established between the frequency of the input sine wave and the sampling frequency of the DAC. For this reason, an arbitrary frequency cannot be selected as the testing frequency. In addition, a very large number of samples are required for any technique chosen. Assuming a number of samples equal to 512, the volume of computation needed is as follows:
FFT approach: 4092 real number multiplications and 7668 real number additions;
curve fitting approach: 6656 real number multiplications and 4092 real number additions.
It is a first object of the present invention to provide an ADC evaluation system which is capable of independently dealing with individual factors of a compounded fault and of enabling an estimation of an instantaneous effective number of bits.
It is a second object of the present invention to provide a system for evaluation of an effective number of bits of an ADC which permits an arbitrary choice of a testing frequency.
It is a third object of the present invention to provide a system for evaluating the effective number of bits of an ADC which can be implemented by simple hardware.
It is a fourth object of the present invention to provide an ADC evaluation system which is capable of estimating the effective number of bits with high accuracy without increasing the length of testing time.
It is a fifth object of the present invention to provide an ADC evaluation system capable of observing an instantaneous effective number of bits as a function of time.
It is a sixth object of the present invention to provide a DAC evaluation system which is capable of independently dealing with individual factors of a compounded fault and enabling an estimation of an instantaneous effective number of bits.
It is a seventh object of the present invention to provide a system for evaluating the effective number of bits for DAC in which an arbitrary choice of a testing frequency is allowed.
It is an eighth object of the present invention to provide a system for evaluating the effective number of bits of a DAC which can be implemented by simple hardware.
It is a ninth object of the present invention to provide a DAC evaluation system which is capable of estimating the effective number of bits with high accuracy without increasing the length of testing time.
It is a tenth object of the present invention to provide a DAC evaluation system which permits an instantaneous observation of an effective number of bits as a function of time.
In order to accomplish the above objects, in the first aspect of the present invention, there is provided an evaluation system for an A-D converter comprising: a signal generator for generating an analog signal corresponding to a sine wave; a timing controller for generating a clock which is used in supplying an analog signal to an A-D converter under test; a waveform memory for storing and accumulating a digital signal outputted from the A-D converter; instantaneous amplitude calculation means for taking out a digital signal stored in the waveform memory therefrom and determining an instantaneous amplitude; interleave signal producing means for receiving the instantaneous amplitude and the amplitude of the sine wave as its inputs and forming an interleave signal in which the instantaneous amplitude and the amplitude of the sine wave are interleaved;.and digital moving differentiator means for receiving the interleave signal as its input and calculating a moving difference.
In the second aspect of the present invention, there is provided an evaluation system for an A-D converter comprising: a signal generator for generating an analog signal corresponding to a sine wave; a timing controller for generating a clock which is used in supplying an analog signal to an A-D converter under test; a waveform memory for storing and accumulating a digital signal outputted from the A-D converter; instantaneous amplitude calculation means for taking out a digital signal stored in the waveform memory therefrom and determining an instantaneous amplitude; interleave signal producing means for receiving the instantaneous amplitude and the amplitude of the sine wave as its inputs and forming an interleave signal in which the instantaneous amplitude and the amplitude of the sine wave are interleaved; and Wavelet transform means-for receiving the interleave signal as its input and applying a Wavelet transform to the interleave signal.
The evaluation system for an A-D converter may further comprise a digital signal selecting means for selecting and taking out from the waveform memory either a digital signal that corresponds to a cosine wave or a digital signal the applied signal of which corresponds to a sine wave.
The waveform memory may include a plurality of waveform memories for storing and accumulating the digital signal, and the evaluation system for an A-D converter may further comprise: selecting means for selecting a waveform memory which stores and accumulates therein a digital signal corresponding to a cosine wave or a digital signal corresponding to a sine wave; and read-out means for selecting a waveform memory to read out the digital signal stored and accumulated therein.
The evaluation system for an A-D converter may further comprise: a trigger circuit coupled to a write circuit for the waveform memory and generating a trigger signal under a specified condition of an input digital signal; and control means for taking in a given quantity of digital signals on the basis of the trigger signal from the trigger circuit.
The instantaneous amplitude calculation means may comprise: multiplication means for reading a plurality of digital signals from the waveform memory to derive a square signal of a digital signals corresponding to the cosine wave and a square signal of a digital signal corresponding to the sine wave; adder means for adding a plurality of square signals to derive a square amplitude signal; and square root means for forming a square root of the square amplitude signal to determine an instantaneous amplitude signal.
The digital moving differentiator means may further comprise a combination of absolute value calculating means for determining an absolute value of a difference signal and maximum value detecting means for receiving an absolute value signal as its input and detecting the maximum value thereof.
The digital moving differentiator means may further comprise: a period memory which stores the period of a sine wave being applied to the A-D converter; and a combination of absolute value calculating means for determining an absolute value of a difference signal, and maximum value detecting means for receiving an absolute value signal as its input and detecting a-maximal value thereof in correspondence to the period of the sine wave.
The Wavelet transform means may further comprise a combination of absolute value calculating means for determining an absolute value of a signal obtained as a result of the Wavelet transform, and maximum value detecting means for receiving an absolute value signal as its input and detecting the maximum value thereof.
The Wavelet transform means may further comprise: a period memory which stores the period of a sine wave being applied to the A-D converter; and a combination of absolute value calculating means for determining an absolute value of a signal obtained as a result of the Wavelet transform, and maximal value detecting means for receiving an absolute value signal as its input and detecting a maximal value thereof in correspondence to the period of the sine wave.
In the third aspect of the present invention, there is provided an evaluation system for a D-A converter comprising: a pattern generator for generating a sine wave pattern in the form of a digital signal; a timing controller for generating a clock which is used in supplying the sine wave pattern to a D-A converter under test; an A-D converter having a higher accuracy of conversion than the D-A converter and operative to convert an analog signal outputted from the D-A converter to a digital signal; a waveform memory for storing and accumulating a digital signal outputted from the A-D converter; instantaneous amplitude calculation means for taking out a digital signal stored in the waveform memory therefrom and determining an instantaneous amplitude; interleave signal producing means for receiving the instantaneous amplitude and the amplitude of the sine wave as its inputs and forming an interleave signal in which the instantaneous amplitude and the amplitude of the sine wave are interleaved; and digital moving differentiator means for receiving the interleave signal as its input and calculating a moving difference.
In the fourth aspect of the present invention, there is provided an evaluation system for a D-A converter comprising: a pattern generator for generating a sine wave pattern in the form of a digital signal; a timing controller for generating a clock which is used in supplying the sine wave pattern to a D-A converter under test; an A-D converter having a higher accuracy of conversion than the D-A converter and operative to convert an analog signal outputted from the D-A converter to a digital signal; a waveform memory for storing and accumulating a digital signal outputted from the A-D converter; instantaneous amplitude calculation means for taking out a digital signal stored in the waveform memory therefrom and determining an instantaneous amplitude; interleave signal producing means for receiving the instantaneous amplitude and the amplitude of the sine wave as its inputs and forming an interleave signal in which the instantaneous amplitude and the amplitude of the sine wave are interleaved; and Wavelet transform means for receiving the interleave signal as its input and applying a Wavelet transform to the interleave signal.
The evaluation system for a D-A converter may further comprise a digital signal selecting means for selecting and taking out from the waveform memory either a digital signal that corresponds to a cosine wave or a digital signal that corresponds to a sine wave.
The waveform memory may include a plurality of waveform memories for storing and accumulating the digital signal, and the evaluation system for a D-A converter may further comprise: selecting means for selecting a waveform memory which stores and accumulates therein a digital signal pattern corresponding to a cosine wave or a digital signal pattern corresponding to a sine wave; and read-out means for selecting a waveform memory to read out the digital signal stored and accumulated therein.
The evaluation system for a D-A converter may further comprise: a trigger circuit coupled to a write circuit for the waveform memory and generating a trigger signal under a specified condition of an input digital signal pattern, and control means for taking in a given quantity of digital signals on the basis of the trigger signal from the trigger circuit.
The instantaneous amplitude calculation means may comprises: multiplication means for reading a plurality of digital signals from the waveform memory to derive a square signal of a digital signals corresponding to the cosine wave and a square signal of a digital signal corresponding to the sine wave; adder means for adding a plurality of square signals to derive a square amplitude signal; and square root means for forming a square root of the square amplitude signal to determine an instantaneous amplitude signal.
The digital moving differentiator means may further comprise a combination of absolute value calculating means for determining an absolute value of a difference signal and maximum value detecting means for receiving an absolute value signal as its input and detecting the maximum value thereof.
The digital moving differentiator means may further comprise: a period memory which stores the period of a sine wave being applied to the D-A converter; and a combination of absolute value calculating means for determining an absolute value of a difference signal, and maximum value detecting means for receiving an absolute value signal as its input and detecting a maximal value thereof in correspondence to the period of the sine wave.
The Wavelet transform means may further comprise a combination of absolute value calculating means for determining an absolute value of a signal obtained as a result of the Wavelet transform, and maximum value detecting means for receiving an absolute value signal as its input and detecting the maximum value thereof.
The Wavelet transform means may further comprise: a period memory which stores the period of a sine wave being applied to the D-A converter; and a combination of absolute value calculating means for determining an absolute value of a signal obtained as a result of the Wavelet transform, and maximal value detecting means for receiving an absolute value signal as its input and detecting a maximal value thereof in correspondence to the period of the sine wave.